1. Technical Field
Embodiments described herein relate generally to a semiconductor integrated circuit and, more particularly, to a semiconductor integrated circuit capable of controlling a read command.
2. Background
Typically, a semiconductor integrated circuit operates by synchronizing a command signal and an address with the rising edge of a clock. The trend towards an increase in data bandwidth has a tradeoff in that the number of pins required by the semiconductor integrated circuit is increased. Since a reduced number of pins can be considered beneficial, techniques for achieving such results have been considered.
For example, the use of a multiplexing scheme for the pins has been considered. In this scheme multi-addressing can be performed relative to one address pin using rising and falling edges of a clock. For example, the address pin is used as a first address at the rising edge of the clock, and if the address pin is synchronized with the falling edge of the clock, the address pin can be used as a tenth address. In this way, the requisite number of pins can be partially reduced.
However, a semiconductor integrated circuit typically starts a read or write operation at a subsequent rising edge occurring after multi-addressing is performed twice after an external read or write command is applied to the semiconductor integrated circuit. Thus an address access time (tAA) may be increased in a scheme for reducing the number of requisite pins.